This invention relates to memory access and more particularly to an improved burst access operation to include fast access to words on the same row (wordline) in memory.
A flash memory bank has a dedicated synchronous read port interface which facilitates read access from main flash memory. Referring to FIG. 1 there is illustrated a block diagram of a flash memory bank 21 and a read interface (control logic) 10 responsive to signals from an interface bus which communicates with the host. The interface bus consists of an address bus, a data bus, and several control signals. The width of the address bus is dependent on the number of words in the associated flash and the width of the data read port interface. A host provides an address AR and an address valid signal ADVZ for standard accesses. Standard read refers to random accesses anywhere in the address space of the flash bank. A read port interface synchronizes the access to the system clock SYSCLOCK. Two ready signals (READY and PREADY), one a pipelined version of the other, are generated in the read port interface, to signal that data is available to the host. The flash bank read interface has internal wait state generation to create these signals. All outputs from the read ports are generated on the rising edges of the system clock with the exception of the output data. Output data is passed directly from the flash bank to the bus interface.
Table 1 shows the read port signals. In the prior art this port supports two modes of read operations: standard and burst. Burst according to the prior art read refers to a mode in which sequential addresses are generated in the read port interface. Burst read enables the potential for a higher data rate when accesses occur on the same wordline within the flash bank, increasing system performance. Access time within the flash bank can be faster within a wordline (also called page) because the same wordline drive is active as the previous access. If the access is from a different wordline the current wordline must be deactivated and a different wordline activated, which takes a finite amount of time which is longer than an access from the same page. Burst reads are enabled by an additional control input, BAAZ. When burst is active the flash read port interface generates subsequent addresses, including transitions across wordline boundaries (the read port interface automatically adds wait states, as needed). In the read port interface implementation there are two wait state counters, one for a normal read which may occur on any wordline randomly, and one for a page read which occurs on the same wordline as the previous read. The page read wait state count is typically smaller than the normal read wait state count.
As previously mentioned, standard (random access) and burst access (read port interface generates sequential accesses with address override) are supported. Module data outputs, DR(y:0) busses, are driven by the banks directly.
The flash module standard read timing is shown in FIG. 2. The read is synchronous, requiring the flash system clock and an Address Valid (ADVZ) to properly time wait state generation and ready signal synchronization. The clock is input via the control port. The flash read port interface latches the address on the rising edge of the clock while ADVZ is active low. The clock rising edge triggers the wait state counter. Once the number of wait states has elapsed READY goes high for one clock cycle. READY, when active high, allows the host to latch output data on the next rising edge of the clock. The READY signal becomes active for one cycle after the required number of wait states have been inserted. All standard reads use the WTREAD count for wait state generation. This is the normal read wait state count. The example in FIG. 2 has two wait states. In the example, the latched address bus internal to the read port interface is shown for reference, as are the arrows on SYSCLOCK, which shows when addresses and/or data are latched. A pipelined version of READY called PREADY is also generated in the read port interface. PREADY is active the clock cycle before READY is active when the number of wait states is one or greater. Note that for zero wait states PREADY will always remain low.
A standard burst operation, especially in slower memories such as flash or FeRAM, allows sequential accesses on the same physical row in memory to be accessed faster than a random access because the wordline does not need to be activated before the read, as previously stated. It is activated from the prior read. In the prior art this kind of address generation is done to allow sequential accesses only if the memory locations are accessed in consecutive order. It is desirable to provide a system where the addresses need not be consecutive, but only on the same wordline.
In accordance with one embodiment of the present invention an interface allows, after issuance of an address, the detection of whether the current access is on the same physical memory row as the previous address, and accordingly allows a different number of wait states, depending on whether the access is on the same row or a different row. In accordance with an embodiment, the faster access time is available if the address for the current access is either generated by a counter in the interface or supplied by a host system on the address input to the interface. The host system provides a control signal to the interface to select whether the memory interface should use the address from the counter or from the interface""s address input.